2D-characterization and optimization of a basic switching cell aimed at smart power

This paper presents the two-dimensional characterization and the performance optimization of a basic power switching cell with respect to such features as breakdown voltage, on-resistance, parasitic capacitances and IC die size. This cell implements a low-side/high-side transistor configuration which is merged together with low voltage control and protection circuits to achieve a basic building block aimed at smart power ICs, to be fabricated with standard CMOS technologies and rated at up to 20 W. Transistors are based on the lightly doped concept to attain breakdown voltages far beyond conventional values. The optimization of the basic cell is carried out with the support of the two-dimensional simulator SPISCES. By these means, it was possible to achieve significant improvements in the electrical characteristics of the devices and performance of the switching cell. Finally, the simulation results are presented and compared with the available experimental data. New design strategies in what concerns cell geometry are proposed