A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement

This paper presents a high-speed digital feedforward delta-sigma modulator which relaxes timing requirement for the dynamic element matching (DEM) algorithm. By making the main digital to analog converter (DAC) process a small part of the input signal, the distortion from the DAC is suppressed. The proposed method allows eliminating the DEM circuitry in the critical data path for high-speed applications, thus achieving high-resolution without augmenting considerable silicon area. Analysis and simulation results verify the effectiveness of the proposed method.