Static noise margin and soft-error rate simulations for thin film transistor cell stability in a 4 Mbit SRAM design

The thin film transistor (TFT) cell stability has been investigated by simulating Static Noise Margin (SNM) and Soft-Error Rate (SER) of a 4 Mbit SRAM which features a symmetrical spilt word-line bit cell in a double metal, quadruple poly 0.35 μm CMOS process. The correlation of SNM to cell-ratio (γ) and power supply voltage (V _cc) can determined the width of drive transistor for a bit cell area minimization. By using 3D simulation, we extract the parasitic cell capacitances associated with storage node, bit-line, word-line, and TFT-load to evaluate dynamic stability with SER simulation. For a typical alpha-particle incidence, we applied an exponential-like waveform on high voltage storage node at three different transient phases such as writing, reading, and data retention periods in a memory cell in HSPICE simulation. The most vulnerable period by alpha particle injection has been found at just after the writing period