Low power and low voltage considerations in the design of a high frequency clock generator

Author

Shamsi, Hossein ; Shoaei, O. ; Zahabi, A. ; Koolivand, Y. ; Doost, R.

Author_Institution

ECE Dept., Tehran Univ., Iran

Volume

2

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

933

Abstract

A low voltage, 1.2 V, 4 GHZ CMOS phase lock loop for clock generation is reported. This low voltage clock generator consists of a ring oscillator as the VCO that works from 100 MHz to 4 GHZ with a maximum power consumption of 11 mW. Employing a charge pump circuit with suitable loop filter, a ripple free control voltage is provided for VCO. The total power consumption of this PLL, simulated in a 0.13 μm CMOS technology, is about 54 mW.

Keywords

CMOS integrated circuits; clocks; integrated circuit design; low-power electronics; phase locked loops; pulse generators; voltage-controlled oscillators; 0.13 micron; 1.2 V; 100 to 4 GHz; 11 mW; 54 mW; CMOS phase lock loop; CMOS technology; PLL; VCO; charge pump circuit; high frequency clock generator; integrated circuit design; loop filter; low power electronics; low voltage electronics; power consumption; ring oscillator; CMOS technology; Charge pumps; Circuits; Clocks; Energy consumption; Frequency; Low voltage; Power generation; Ring oscillators; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1413033

Filename

1413033