A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration

Digital phase-locked loops (DPLLs) have recently emerged as a viable alternative to classical charge-pump analog PLLs. By obviating the need for a large loop filter capacitor and a high-performance charge pump, DPLLs offer area savings and easier scalability to newer processes. The ability to reconfigure the digital loop filter dynamically offers flexibility in setting the loop response and helps to optimize the locking behavior of the DPLL. However, conflicting bandwidth requirements to simultaneously suppress TDC quantization error and oscillator phase noise mandate either a high-resolution TDC or a low-noise oscillator to minimize jitter. Further, much like in an analog PLL, the ring oscillator is susceptible to supply noise, which especially limits the jitter performance of a DPLL integrated into a large digital system. A low-dropout regulator is commonly used to shield the DCO from supply noise at the expense of additional area, power, and voltage headroom. Alternatively, an open-loop supply-noise cancellation scheme can operate at a lower supply voltage, but its accuracy is highly sensitive to process variations. Analog foreground calibration compensates for process variation but is susceptible to voltage, temperature, and frequency variations. In this paper, we present a deterministic test-signal-based back ground calibration scheme that leverages the highly digital nature of the DPLL to adaptively cancel the supply noise in the DCO. The prototype DPLL achieves nearly perfect supply-noise cancellation over an output frequency range of 0.4 to 3GHz while consuming 2.65mW at 1.5GHz.