CMOS Limiting Amplifier and RSSI (Received Signal Strength Indicator)

Design of CMOS limiting amplifier and Received signal strength indicator presents the analysis and the optimization of a limiting amplifier with received signal strength indicator realized in a standard technique of CMOS process. The limiter works at a supply voltage of 2.0V and at a frequency of 10.7 MHz.. The optimal power consumption for specified speed, overall gain, and accuracy is determined by the limiting amplifier and RSSI. The offset subtractor is used to reduce the offset which is arise due to the cross connected source coupled pair. Also the FWR is used for current rectification and summation in the RSSI. The RSSI stages rectify the signals from each stage and change the signal to a current. The output of each stage of the RSSI are fed to a resistor to ground, which performs a summing operation. Furthermore various simulation methods are used in order to guarantee the functionality of the circuit under all conditions of work.