Design and Implementation of the Low Power 0.64mW, 380 KHz Continuous Time Sigma Delta ADC

Author

Kanhe, Aniruddha ; Acharya, Bibhudendra ; Deshmukh, R.B.

Author_Institution

Dept. of Electron. & Telecommun., NIT, Raipur, India

fYear

2011

fDate

18-20 Nov. 2011

Firstpage

280

Lastpage

283

Abstract

In this paper a low power Sigma Delta Modulator is presented. The reported ADCs which are used in high bandwidth applications ranging from KHz to MHz consume about 10 to 70mW. The modulator designed in this work consumes 0.64mW from a 1.8V supply and operates at 380 KHz with an over-sampling ratio of 64 and a single bit quantizer in 180nm technology for portable and digital radio application. Discrete-time and continuous-time sigma-delta modulators are compared to highlight the power advantages and design challenges in the continuous-time approach. For testing purpose the coherent sampling is done to get the FFT plot of the output signal.

Keywords

fast Fourier transforms; low-power electronics; sigma-delta modulation; FFT plot; coherent sampling; continuous time sigma delta ADC; continuous-time sigma-delta modulator; digital radio application; discrete-time sigma-delta modulator; frequency 380 kHz; low power sigma delta modulator; over-sampling ratio; portable radio application; power 0.64 mW; power 10 mW to 70 mW; single bit quantizer; size 180 nm; voltage 1.8 V; Bandwidth; Clocks; Frequency modulation; Power demand; Sigma delta modulation; Transfer functions; Low power; Op-amp; SNR; Sigma Delta ADC;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Trends in Engineering and Technology (ICETET), 2011 4th International Conference on

Conference_Location

Port Louis

ISSN

2157-0477

Print_ISBN

978-1-4577-1847-2

Type

conf

DOI

10.1109/ICETET.2011.68

Filename

6120597