Title :
A direct digital frequency synthesizer with minimized tuning latency of 12ns
Author :
Willson, Alan ; Ojha, Mukund ; Agarwal, Shilpa ; Lai, Thriven ; Kuo, Tzu-chieh
Author_Institution :
Univ. of California, Los Angeles, CA, USA
Abstract :
A downside for all direct digital synthesizer (DDS) architectures is that every DDS has a phase accumulator (PA) whose normalized phase value φ must be updated for each (sin 2πφ, cos 2πφ) output-pair produced, and such updating introduces a rather long carry-ripple. PA lengths of 32-b are commonplace and 48-b or longer PA can be found in commercial DDS products. When a DDS with high data-rate is needed, the long PA carry-ripple can present a serious bottle neck-one usually overcome by some form of PA pipelining-but then, only at the cost of a significant increase in "tuning latency" as well as added power consumption and chip-area. Ref. [1] explains how (for a mere 24-b PA) such pipelining introduces a 55-cycle latency, setting the system\´s frequency-hopping limit at 700/55 = 12.7MHz, for a DDS generating outputs at 700MHz. All such PA pipelining difficulties are completely eliminated by the architecture reported here.
Keywords :
circuit tuning; direct digital synthesis; PA pipelining; carry-ripple; chip-area; direct digital frequency synthesizer; frequency 12.7 MHz; frequency 700 MHz; frequency-hopping limit; normalized phase value; phase accumulator; power consumption; time 12 ns; tuning latency; word length 32 bit; word length 48 bit; CMOS integrated circuits; Computer architecture; Frequency synthesizers; Pipeline processing; Signal to noise ratio; Solid state circuits; Synthesizers;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-61284-303-2
DOI :
10.1109/ISSCC.2011.5746254
