A Noise Reduced Digitally Controlled Oscillator Using Complementary Varactor Pairs

This paper presents a noise reduced digitally controlled oscillator (DCO) using complementary varactor pairs for PHS transceivers. Due to some modifications on the varactors, reduced phase noise and increased frequency resolution are obtained for our DCO. The DCO is designed in a 0.18 mum CMOS process with a central running frequency of 3.8GHz and over 1GHz tuning range. Simulation results show that the phase noise at 1.2MHz offset frequency is below -123dBc/Hz while drawing only 2.8mA of current from a 1.8V supply. It demonstrates that our DCO achieves improved phase noise and power consumption while its performance has no dependence on the feature size of the given process.