Title :
A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC
Author :
Abdollahi-Alibeik, Shahram ; Weber, David ; Dogan, Hakan ; Si, William W. ; Baytekin, Burcin ; Komijani, Abbas ; Chang, Richard ; Vakili-Amini, Babak ; Lee, MeeLan ; Gan, Haitao ; Rajavi, Yashar ; Samavati, Hirad ; Kaczynski, Brian ; Lee, Sang-Min ; Limot
Author_Institution :
Atheros Commun., San Jose, CA, USA
Abstract :
The rapid commercialization of the IEEE 802.11n WLAN standard has increased the demand for higher data-rate and longer-range fully integrated MIMO SoCs that are backward-compatible with legacy IEEE 802.11a/b/g networks. This paper introduces a 3-stream, 3x3 MIMO WLAN SoC that utilizes three antennas to improve throughput, range, and link robustness. This chip integrates three dual-band transceivers, digital physical layer, media access controller, and a PCI express interface in a 65nm CMOS process. Improved EVM is achieved by reducing transmit and receive l/Q mismatch with calibration, and reducing the integrated phase noise with a reference clock doubler.
Keywords :
IEEE standards; MIMO communication; antennas; phase noise; system-on-chip; telecommunication standards; wireless LAN; IEEE 802.11n WLAN standard; antennas; dual-band 3-stream 802.11n MIMO WLAN SoC; phase noise reduction; reference clock doubler; size 65 nm; Calibration; Clocks; MIMO; Radio frequency; Receivers; System-on-a-chip; Wireless LAN;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-61284-303-2
DOI :
10.1109/ISSCC.2011.5746268
