Character recognition with CMAC on field programmable gate array

Author

Liu, Shao-Han ; Lin, Jzau-Sheng ; Huang, Shih-Yuang

Author_Institution

Dept. of Electron. Eng., Nat. Chin-Yi Inst. of Technol., Taichung, Taiwan

Volume

2

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

1109

Abstract

We proposed a cerebellar model arithmetic computer (CMAC) neural network to characters recognition on an FPGA architecture. The CMAC has many advantages in terms of speed of operation based on LMS training. Its ability realizes arbitrary nonlinear mapping and a fast practical hardware implementation. This work presents CMAC hardware that is about 35 times faster than that by the software executed on the conventional processor. In the experimental results, the CMAC is shown that it can clearly distinguish 94 characters with a size of 8×8 pixels though there are some noise pixels in a character.

Keywords

cerebellar model arithmetic computers; field programmable gate arrays; learning (artificial intelligence); least mean squares methods; optical character recognition; CMAC neural network; FPGA architecture; LMS training; cerebellar model arithmetic computer; character recognition; field programmable gate array; hardware implementation; noise pixels; nonlinear mapping; Associative memory; Brain modeling; Character recognition; Computer networks; Digital arithmetic; Field programmable gate arrays; Hardware; Mathematical model; Neural networks; Pattern recognition;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1413078

Filename

1413078