Title :
Parasitic effects in integrated circuits
Author_Institution :
Motorola Semiconductor Products, Inc., Phoenix, AZ, USA
Keywords :
Circuit optimization; Circuit testing; Diffusion processes; Epitaxial layers; Fabrication; P-n junctions; Parasitic capacitance; Resistors; Silicon; Substrates;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1963 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1963.1157449
