An 8MB level-3 cache in 32nm SOI with column-select aliasing

High-performance multi-core processors require efficient multi-level cache hierarchies to meet high-bandwidth data requirements. Because level-3 (L3) cache is typically the largest cache on the die, the drive to lower cost places pressure on density, yields, and test time. Performance-per-watt goals and total power constraints also compel a variety of circuit techniques to reduce power. The next generation server processor codenamed "Orochi", implemented on a 32nm high-k metal-gate SOI process with 11 metal layers, consists of four 2-core modules using AMD\´s next-generation architecture, code named "Bulldozer", with 2MB of dedicated L2 cache per module and an 8MB shared L3 cache.