CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures

Author

Putnam, Andrew ; Bennett, Dave ; Dellinger, Eric ; Mason, Jeff ; Sundararajan, Prasanna ; Eggers, Susan

Author_Institution

Dept. of Comput. Sci. & Eng., Univ. of Washington, Seattle, WA

fYear

2008

fDate

8-10 Sept. 2008

Firstpage

173

Lastpage

178

Abstract

This paper describes CHiMPS, a C-based accelerator compiler for hybrid CPU-FPGA computing platforms. CHiMPSpsilas goal is to facilitate FPGA programming for high-performance computing developers. It inputs generic ANSIC code and automatically generates VHDL blocks for an FPGA. The accelerator architecture is customized with multiple caches that are tuned to the application. Speedups of 2.8x to 36.9x (geometric mean 6.7x) are achieved on a variety of HPC benchmarks with minimal source code changes.

Keywords

compiler generators; field programmable gate arrays; hardware description languages; C-based accelerator compiler; C-level compilation flow; CHiMPS; FPGA programming; VHDL blocks; generic ANSIC code; hybrid CPU-FPGA architectures; multiple caches; source code; Costs; Field programmable gate arrays; Hardware design languages; High level languages; Logic devices; Parallel processing; Pipeline processing; Programmable logic arrays; Programming profession; Reconfigurable logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on

Conference_Location

Heidelberg

Print_ISBN

978-1-4244-1960-9

Electronic_ISBN

978-1-4244-1961-6

Type

conf

DOI

10.1109/FPL.2008.4629927

Filename

4629927