DocumentCode
2894956
Title
Low-offset comparator using capacitive self-calibration
Author
Lei Sun ; Kong-Pang Pun
Author_Institution
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Hong Kong, China
fYear
2012
fDate
4-7 Nov. 2012
Firstpage
412
Lastpage
414
Abstract
A new high-precision self-calibrated comparator for high resolution converters is presented. It uses a bridged-capacitor array as the calibration digital-to-analog converter (DAC) for high power efficiency and low noise. Post-layout simulations in a 1.8V 0.18μm CMOS show that the comparator achieves a less than 50μV offset for a 14-bit target resolution while consumes only 45μW at the frequency period of 300ns.
Keywords
CMOS integrated circuits; bridge circuits; circuit layout; comparators (circuits); digital-analogue conversion; CMOS; DAC; bridged-capacitor array; capacitive self-calibration; digital-to-analog converter; high resolution converters; low-offset comparator; post-layout simulations; self-calibrated comparator; Arrays; Calibration; Capacitance; Capacitors; Noise; Power dissipation; Transistors; Analog-to-Digital Converters; comparator; low offset; self-calibration;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2012 International
Conference_Location
Jeju Island
Print_ISBN
978-1-4673-2989-7
Electronic_ISBN
978-1-4673-2988-0
Type
conf
DOI
10.1109/ISOCC.2012.6406883
Filename
6406883
Link To Document