Energy and area analysis of a floating-point unit in 15nm CMOS process technology

Author

Salehi, Soheil ; DeMara, Ronald F.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Central Florida, Orlando, FL, USA

fYear

2015

fDate

9-12 April 2015

Firstpage

1

Lastpage

5

Abstract

The continuous increase in transistor density based on Moore´s Law has led us to Complementary Metal-Oxide Semiconductor (CMOS) technologies beyond 45nm process node. These highly-scaled process technologies offer improved density as well as a reduction in nominal supply voltage. New challenges also arise, such as relative proportion of leakage power in standby mode. In this paper, we present an analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies. For this purpose, an IEEE 754 Single Precision Floating-Point Unit implementation is analyzed based on 45nm and 15nm technologies. The results have shown that using the 15nm technology we can have 4 times less energy and 3-fold smaller footprint.

Keywords

CMOS digital integrated circuits; floating point arithmetic; power consumption; CMOS process technology; IEEE 754; Moores law; area analysis; complementary metal-oxide semiconductor technology; energy analysis; leakage power; power consumption; single precision floating-point unit; size 15 nm; size 45 nm; transistor density; CMOS integrated circuits; FinFETs; Libraries; Logic gates; Power demand; Reliability; Standards; 15nm process technology; CMOS technology; Floating-Point; IEEE 754; Predictive Technology Model; energy aware design;

fLanguage

English

Publisher

ieee

Conference_Titel

SoutheastCon 2015

Conference_Location

Fort Lauderdale, FL

Type

conf

DOI

10.1109/SECON.2015.7132972

Filename

7132972