Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS

Author

Waheed, Khurram ; Staszewski, Robert Bogdan

Author_Institution

Wireless Analog Technol. Center, Texas Instruments, Dallas, TX

fYear

2007

fDate

27-30 May 2007

Firstpage

1253

Lastpage

1256

Abstract

The paper proposed estimation techniques and compensation algorithms against CMOS device variability in an all-digital RF polar transmitter. The transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency/phase and amplitude analog domains. The converters built with segmented banks consist of a large number of unit-weighted devices which exhibit a certain level of random and systematic mismatch. The techniques presented are employed in a commercial single-chip GSM/EDGE radio realized in 90 nm CMOS

Keywords

CMOS integrated circuits; cellular radio; compensation; estimation theory; transmitters; 90 nm; CMOS device variability; all-digital RF polar transmitter; compensation algorithms; device mismatch tolerant transmitters; digital RF processing techniques; estimation techniques; nanometer-scale CMOS; single-chip GSM/EDGE radio; Amplitude modulation; Analog-digital conversion; CMOS logic circuits; CMOS process; Digital-to-frequency converters; Logic devices; Nanoscale devices; Phase modulation; Radio frequency; Radio transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378338

Filename

4252873