DocumentCode
2895292
Title
An FPGA-based high-speed, low-latency trigger processor for high-energy physics
Author
De Cuveland, Jan ; Rettig, Felix ; Angelov, Venelin ; Lindenstruth, Volker
Author_Institution
Kirchhoff-Inst. for Phys., Univ. of Heidelberg, Heidelberg
fYear
2008
fDate
8-10 Sept. 2008
Firstpage
293
Lastpage
298
Abstract
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high bandwidth (2.16 Tbit/s), low latency, and flexibility in the processing algorithm. The input data come optically via 1 080 links operating at 2.5 Gbit/s. The whole system is partitioned hierarchically in 18 groups of 5+1 modules and one top module. All modules contain the same PCB, FPGA, DDR SRAM and SDRAM, but are equipped with different optional components and additional interface boards, which simplifies the hardware development significantly and reduces the production costs. Embedded PowerPC processors running Linux systems are used to implement a control and monitoring system. The system was installed in the real environment in December 2007 and is in continuous operation for cosmic data taking.
Keywords
Linux; field programmable gate arrays; high energy physics instrumentation computing; microprocessor chips; nuclear electronics; DDR SRAM; FPGA design; Linux systems; PCB; SDRAM; bit rate 2.5 Gbit/s; cosmic data taking; embedded PowerPC processors; high-energy physics; high-speed processor; low-latency trigger processor; Bandwidth; Delay; Field programmable gate arrays; Hardware; High speed optical techniques; Partitioning algorithms; Physics; Production; Random access memory; SDRAM;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on
Conference_Location
Heidelberg
Print_ISBN
978-1-4244-1960-9
Electronic_ISBN
978-1-4244-1961-6
Type
conf
DOI
10.1109/FPL.2008.4629947
Filename
4629947
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