Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec

A Low-Density Parity-Check (LDPC) codec circuit is implemented in a 65nm Low-Power Partially-Depleted SOI (LP PD-SOI) technology, as well as in a "conventional" Low-Power Bulk technology for a fair comparison. PD-SOI allows to increase maximum frequency versus bulk at a given voltage, and to decrease dynamic power versus bulk at a given frequency. Thanks to a digital power switching technique specifically optimized for LP PD-SOI, we demonstrate a leakage current reduction versus bulk 65nm LP implementation, solving one of the most critical problems of PD-SOI technology, as identified in previous publications.