Title :
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec
Author :
Le Coz, Julien ; Flatresse, Philippe ; Engels, Sylvain ; Valentian, Alexandre ; Belleville, Marc ; Raynaud, Christine ; Croain, Damien ; Urard, Pascal
Author_Institution :
STMicroelectronics, Crolles, France
Abstract :
A Low-Density Parity-Check (LDPC) codec circuit is implemented in a 65nm Low-Power Partially-Depleted SOI (LP PD-SOI) technology, as well as in a "conventional" Low-Power Bulk technology for a fair comparison. PD-SOI allows to increase maximum frequency versus bulk at a given voltage, and to decrease dynamic power versus bulk at a given frequency. Thanks to a digital power switching technique specifically optimized for LP PD-SOI, we demonstrate a leakage current reduction versus bulk 65nm LP implementation, solving one of the most critical problems of PD-SOI technology, as identified in previous publications.
Keywords :
CMOS digital integrated circuits; circuit optimisation; codecs; leakage currents; low-power electronics; parity check codes; power semiconductor switches; silicon-on-insulator; LDPC codec; LP PD-SOI; LP bulk; adaptive power gate body bias; digital power-switching technique; leakage current reduction; low-density parity-check codec circuit; low-power bulk technology; low-power partially-depleted SOI technology; size 65 nm; Codecs; Decoding; Leakage current; Parity check codes; Silicon; Switches; Temperature measurement;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-61284-303-2
DOI :
10.1109/ISSCC.2011.5746343
