A 62mV 0.13μm CMOS standard-cell-based design technique using schmitt-trigger logic

In this paper, the authors demonstrate a standard cell-based circuit technique fully operational at supply voltages between 84 mV and 62 mV in standard 0.13 μm bulk CMOS depending on the area overhead invested. Supply voltage reduction is limited by the degradation of the on/off current-ratio of CMOS transistors with decreasing V_DD, causing the leakage currents through the off transistors to be on the same order of magnitude as the drive currents. The result is an output level degradation of logic gates due to a voltage divider-like behavior, an effect emphasized by process variability. In this work, the output level degradation is mitigated by the use of Schmitt trigger structures, which exhibit an effective leakage quenching in the off-path of a gate and have been proposed for low-voltage RAM.