• DocumentCode
    2895407
  • Title

    A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining

  • Author

    Seok, Mingoo ; Jeon, Dongsuk ; Chakrabarti, Chaitali ; Blaauw, David ; Sylvester, Dennis

  • Author_Institution
    Univ. of Michigan, Ann Arbor, MI, USA
  • fYear
    2011
  • fDate
    20-24 Feb. 2011
  • Firstpage
    342
  • Lastpage
    344
  • Abstract
    In this paper, the authors also show how clocking overhead can be reduced through circuit techniques to facilitate super pipelining while process variation is addressed through the use of latch-based design. Additionally, architecture modifications are proposed to improve energy efficiency and throughput. Measurements show that the FFT core consumes 17.7nJ per 1024-pt complex FFT while operating at 30MHz at Vdd=0.27V, demonstrating an improvement over the FFT energy efficiency.
  • Keywords
    CMOS integrated circuits; clock distribution networks; fast Fourier transforms; flip-flops; integrated circuit design; pipeline arithmetic; circuit techniques; clocking overhead; complex FFT core; frequency 30 MHz; latch-based design; super-pipelining; voltage 0.27 V; Clocks; Delay; Energy consumption; Energy efficiency; Latches; OFDM; Pipeline processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-61284-303-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2011.5746346
  • Filename
    5746346
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2895407