A low power 1D-DCT processor for MPEG-targeted real-time applications

Author

Jiang, Min ; Luo, Yuan ; Fu, Xling ; Yang, Bing ; Zhao, Baoying ; Wang, Xin-An ; Sheng, Shimin ; Zhang, Tianyi

Author_Institution

Sch. of Comput. Sci. & Electr. Eng., Peking Univ., Beijing, China

Volume

2

fYear

2004

fDate

26-29 Oct. 2004

Firstpage

682

Abstract

A 1D-DCT processor with parallel pipelined VLSI architecture is designed for MPEG visual and audio applications. The processor is based on distributed arithmetic to obtain low power and high computation efficiency. The simulation with EDA software shows that the pipelined parallel architecture can reach an efficient compromise between hardware cost and computing speed for real-time MPEG-related applications.

Keywords

VLSI; audio coding; data compression; digital signal processing chips; discrete cosine transforms; distributed arithmetic; electronic design automation; integrated circuit design; logic design; multimedia computing; parallel architectures; pipeline processing; real-time systems; video coding; 1D-DCT processor; EDA software; MPEG audio applications; MPEG visual applications; computation efficiency; distributed arithmetic; multimedia processor; parallel architecture; parallel pipelined VLSI architecture; pipelined architecture; real-time applications; Application software; Arithmetic; Computational modeling; Computer architecture; Costs; Distributed computing; Electronic design automation and methodology; Hardware; Parallel architectures; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technology, 2004. ISCIT 2004. IEEE International Symposium on

Print_ISBN

0-7803-8593-4

Type

conf

DOI

10.1109/ISCIT.2004.1413802

Filename

1413802