DocumentCode :
2895507
Title :
SPP1148 booth: Coarse-grained reconfiguration
Author :
Eisenhardt, Sven ; Schweizer, Thomas ; Filho, Julio A de Oliveira ; Oppold, Tobias ; Rosenstiel, Wolfgang ; Thomas, Alexander ; Becker, Jürgen ; Hannig, Frank ; Kissler, Dmitrij ; Dutta, Hritam ; Teich, Jürgen ; Hinkelmann, Heiko ; Zipf, Peter ; Glesner,
Author_Institution :
Dept. of Comput. Eng., Univ. of Tuebingen, Tubingen
fYear :
2008
fDate :
8-10 Sept. 2008
Firstpage :
349
Lastpage :
349
Abstract :
In the last years, aside from fine-grained reconfigurable architectures such as FPGAs, coarse-grained reconfigurable architectures (CGRAs), which typically have building blocks of a fixed bit-width (8 bit, 16 bit, etc.), have gained in importance in academia as well as in industry. CGRAs are usually used for domain-specific computations and have advantages over traditional FPGAs in terms of area and power cost, performance, and reconfiguration time. Thus, architectures with coarse-grained reconfiguration features have also been studied in projects (Sec. 1, 2, 4) within the priority program Reconfigurable Computing Systems and the project CoMap (Sec. 3), which are all sponsored by the German science foundation.
Keywords :
field programmable gate arrays; reconfigurable architectures; FPGA; SPP1148 booth; coarse-grained reconfiguration; domain-specific computations; fine-grained reconfigurable architectures; Computer architecture; Cyclic redundancy check; Energy efficiency; Field programmable gate arrays; Hardware; Information technology; Power system modeling; Reconfigurable architectures; Runtime; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on
Conference_Location :
Heidelberg
Print_ISBN :
978-1-4244-1960-9
Electronic_ISBN :
978-1-4244-1961-6
Type :
conf
DOI :
10.1109/FPL.2008.4629957
Filename :
4629957
Link To Document :
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