SPP1148 booth: Seamless design flow for reconfigurable systems

Author

Schallenberg, Andreas ; Rettberg, Achim ; Nebel, Wolfgang ; Rammig, Franz

Author_Institution

Carl von Ossietzky Univ., Oldenburg

fYear

2008

fDate

8-10 Sept. 2008

Firstpage

351

Lastpage

351

Abstract

Today, using dynamic partial reconfiguration of FPGAs leads to a longer and less predictable design cycle. To improve this, we developed a modelling, simulation, and synthesis framework for partial reconfiguration, named OSSS+R. It reduces design time and hides some of the complexity. The tool PART-E integrates the results into the Xilinx early access partial reconfiguration (EAPR) flow. It eases floorplanning, bus macro instantiation, and bitstream generation. We show OSSS+R modelling, simulation and Part-E in a hands-on fashion. Synthesis to VHDL is demonstrated, too.

Keywords

field programmable gate arrays; reconfigurable architectures; FPGA; OSSS+R; PART-E; SPP1148 booth; VHDL; Xilinx early access partial reconfiguration flow; bitstream generation; bus macro instantiation; dynamic partial reconfiguration; reconfigurable systems; seamless design flow; Circuit simulation; Circuit synthesis; Design methodology; Field programmable gate arrays; Kernel; Libraries; Logic design; Protocols; Reconfigurable logic; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on

Conference_Location

Heidelberg

Print_ISBN

978-1-4244-1960-9

Electronic_ISBN

978-1-4244-1961-6

Type

conf

DOI

10.1109/FPL.2008.4629959

Filename

4629959