A novel charge recovery logic structure with complementary pass-transistor network

This paper presents a new charge recovery logic structure called Complementary Pass-transistor Boost Logic (CPBL). CPBL is a low-power charge recovery logic structure powered by 2-phase non-overlap alternating power clocks and requires no DC power supply. To demonstrate the energy efficiency of CPBL, 4-bit counter is designed to show the energy comparison among CPBL, Complementary Pass-transistor Adiabatic Logic (CPAL) and the conventional static CMOS with 0.18μm process. The simulation results indicate that CPBL implementation reduces about 65% power dissipation compared with the static CMOS counterpart in a range from 50MHz to 500MHz and dissipates about 40% energy with respect to CPAL at 200MHz.