• DocumentCode
    2895731
  • Title

    A Hardware Efficient Very Large Bit Word Binary to Double Base Number System Converter for Encryption Applications

  • Author

    Muscedere, Roberto

  • Author_Institution
    Res. Centre for Integrated Microsyst., Windsor Univ., Ont.
  • fYear
    2007
  • fDate
    27-30 May 2007
  • Firstpage
    1373
  • Lastpage
    1376
  • Abstract
    The double base number system (DBNS) is currently being proposed for use in the computational multipliers of encryption engines. Implementation of these systems is limited as there is no hardware based method to move the large bit words into the DBNS domain. A previously published greedy binary to DBNS converter, designed for DSP applications (up to 24 bit words) is not easily scalable to perform this task as the internal address decodes increase considerably with the input word size. This paper details a modification to this method so it can be scaled to handle large bit words, variable digits, and no representation error with a minimal change in the address decode complexity.
  • Keywords
    cryptography; digital arithmetic; multiplying circuits; computational multiplier; double base number system converter; encryption applications; encryption engines; variable digits; very large bit word binary; Application software; Cryptography; Decoding; Design methodology; Digital signal processing; Engines; Filters; Hardware; Performance gain;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
  • Conference_Location
    New Orleans, LA
  • Print_ISBN
    1-4244-0920-9
  • Electronic_ISBN
    1-4244-0921-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2007.378483
  • Filename
    4252903