Title :
Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory
Author :
Qiu, Meikang ; Wu, Jiande ; Xue, Chun Jason ; Hu, Jingtong Aaron ; Tseng, Wei-Che ; Sha, Edwin H M
Author_Institution :
Dept. of Electr. Eng., Univ. of New Orleans, New Orleans, LA
Abstract :
Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. This paper studies the scheduling and assignment problem on minimizing the total energy consumption while satisfying timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and Scheduling for Loops), is proposed. The algorithm uses loop scheduling and assignment with the consideration of variable partition to find the best configuration for both memory and ALU.
Keywords :
digital signal processing chips; digital storage; parallel memories; processor scheduling; ALU; heterogeneous multibank memory; high-performance DSP processors; loop scheduling; memory bandwidth; multibank on-chip memory; multiple data memory accesses; total energy consumption; type assignment and scheduling for loops; Computer science; Delay; Digital signal processing; Energy consumption; Flow graphs; Memory architecture; Partitioning algorithms; Processor scheduling; Scheduling algorithm; Timing;
Conference_Titel :
Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on
Conference_Location :
Heidelberg
Print_ISBN :
978-1-4244-1960-9
Electronic_ISBN :
978-1-4244-1961-6
DOI :
10.1109/FPL.2008.4629983