A versatile hardware architecture for a CFAR detector based on a linear insertion sorter

Author

Perez-Andrade, Roberto ; Cumplido, Rene ; Feregrino-Uribe, Claudia ; Campo, Fernando Martin Del

Author_Institution

Dept. of Comput. Sci., Nat. Inst. for Astrophys., Opt. & Electron., Puebla

fYear

2008

fDate

8-10 Sept. 2008

Firstpage

467

Lastpage

470

Abstract

This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detectors require sorting, a linear sorter based on a first in first out (FIFO) schema is used. The proposed architecture can be used as a specialized module or co-processor for software defined radar (SDR) applications. The results of implementing the architecture on a field programmable gate array (FPGA) are presented and discussed.

Keywords

field programmable gate arrays; radar receivers; signal detection; CFAR detector; field programmable gate array; first in first out schema; linear insertion sorter; software defined radar; versatile hardware architecture; Computer architecture; Detectors; Field programmable gate arrays; Hardware; Radar antennas; Radar applications; Radar detection; Signal processing algorithms; Sorting; Statistics;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on

Conference_Location

Heidelberg

Print_ISBN

978-1-4244-1960-9

Electronic_ISBN

978-1-4244-1961-6

Type

conf

DOI

10.1109/FPL.2008.4629985

Filename

4629985