• DocumentCode
    2896136
  • Title

    SAT-based resource binding for reducing critical path delays

  • Author

    Seto, Kenshu ; Nonaka, Yuta ; Maruizumi, Takuya ; Shiraki, Yasuhiro

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Musashi Inst. of Technol., Tokyo
  • fYear
    2008
  • fDate
    8-10 Sept. 2008
  • Firstpage
    507
  • Lastpage
    510
  • Abstract
    In this paper, a new function unit binding approach based on SAT is proposed. Differently from previous approaches, which heuristically minimize the total numbers of inputs of multiplexers, the proposed approach generates SAT formulas that constrain the numbers of inputs of specific multiplexers to certain numbers and produces a solution that satisfies the constraints with a SAT solver. The proposed approach is applied to constrain the numbers of inputs of the multiplexers that lie between the input and output registers of multipliers, since these multiplexers are likely to be on critical paths. Experimental comparisons with a traditional approach show that the proposed approach is promising for reducing critical path delays.
  • Keywords
    computability; critical path analysis; high level synthesis; multiplexing equipment; multiplying circuits; SAT-based resource binding; critical path delays; function unit binding; multiplexers; Delay;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on
  • Conference_Location
    Heidelberg
  • Print_ISBN
    978-1-4244-1960-9
  • Electronic_ISBN
    978-1-4244-1961-6
  • Type

    conf

  • DOI
    10.1109/FPL.2008.4629995
  • Filename
    4629995