• DocumentCode
    2896191
  • Title

    A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS

  • Author

    Abiri, Behrooz ; Sheikholeslami, Ali ; Tamura, Hirotaka ; Kibune, Masaya

  • Author_Institution
    Univ. of Toronto, Toronto, ON, Canada
  • fYear
    2011
  • fDate
    20-24 Feb. 2011
  • Firstpage
    436
  • Lastpage
    438
  • Abstract
    ADC-based receivers allow for extensive equalization in the digital domain and therefore can easily compensate for channel loss at higher data rates. Digital equalization can be implemented as an FFE or DFE. An adaptive FFE is straight forward to implement, as it relies on magnitudes only (not phases) of the blind samples, however, it enhances the quantization noise of the ADC. A DFE has better noise immunity, but challenges remain in designing an adap tive DFE for receivers with blind clocks. A typical adaptive engine for a DFE com pares the equalized center samples against a desired level to calculate error in each sample. The power of this error is then minimized to guide equalization. In a blind receiver, however, the center samples are not known; the blind samples may deviate from the eye´s center and move closer to the zero crossings. As a result, one cannot use a single desired level independent of the blind sampling phase; the desired level must change according to the sampling phase. In this paper, we use a desired waveform, instead of a desired level, to perform the adaptation. Our measurement results confirm that this approach adapts the coefficients within 80μs and opens an otherwise closed eye for a channel atten uation of 13.3dB at 2.5GHz.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; clock and data recovery circuits; decision feedback equalisers; ADC-based receivers; CDR; CMOS; DFE; analogue-digital converters; bit rate 5 Gbit/s; blind clocks; blind receiver; clock and data recovery circuits; decision feedback equalisers; digital equalization; frequency 2.5 GHz; quantization noise; size 65 nm; time 80 mus; Adaptive equalizers; CMOS integrated circuits; Clocks; Decision feedback equalizers; Engines; Receivers; Signal generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-61284-303-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2011.5746386
  • Filename
    5746386