A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery

A clock and data recovery (CDR) circuit is the key building block in all serial communication systems. A classical CDR is implemented using a Type-2 phase locked loop (PLL) wherein a passive lead-lag analog loop filter is used to set the loop response. Large capacitors needed to achieve low jitter transfer bandwidth and a highly over-damped response to reduce jitter peaking prohibit monolithic integration of the analog loop filter. Digital loop filters (DLFs) that are robust to process and temperature variations have recently emerged as an alternate solution to implementing fully integrated CDRs.