A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit

As the panel technology continues to offer displays with higher resolution, greater color depth, and increased frame rate, the amount of video data to display driver ICs (DDIs) inside the panel keeps on expanding. Since the conventional intra-panel interfaces with multi-drop configurations, such as RSDS and mini-LVDS, increase the cost of overall systems at high bandwidth, new intra panel interfaces have been proposed to meet the bandwidth requirement with point-to-point configurations. This paper presents a new high-speed video interface that offers significant complexity reduction in the receiver. It is because receivers are integrated in a DDI with relatively slow high-voltage processes, while transmitters in host controllers are implemented with the more advanced deep-submicron processes. Compared to the PLL-based clock recovery circuits in [K. Yamguchi et al., 2009; I. Jung et al., 2009], the DLL-based data recovery circuit occupies a smaller area with lower power consumption and offers unconditionally stable characteristics along with higher jitter tolerance.