Efficient parallel VLSI architecture for linear feedback shift registers

Linear feedback shift register (LFSR) is an important part of the cyclic redundancy check (CRC) operations and BCH encoders. This paper presents a novel high speed parallel LFSR architecture based on parallel Infinite Impulse Response (IIR) filter design, pipelining and retiming algorithms. A new formulation is proposed to modify the LFSR into the form of an IIR filter. Then pipelining and retiming algorithms are applied to further reduce the critical path in the parallel architecture. A comparison between the proposed and previous architectures shows that our parallel architecture achieves a critical path same as that of previous designs with a reduced hardware cost.