A 1.7mW 11b 1–1–1 MASH ΔΣ time-to-digital converter

Recently, high-resolution TDCs have gained more and more popularity due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs, pipeline TDCs, and SAR TDCs. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay. In order to achieve sub-gate-delay resolution, the Vernier method is commonly used. However, the mismatch problem caused by process variation limits its effectiveness, and the same holds for the time amplification method. The gated-ring-oscillator (GRO) method is introduced to achieve sub-ps time resolution, but it still requires an equivalent CMOS gate delay as low as 6ps. Upcoming applications in 4,h-generation nuclear reactors, space, and high-energy physics such as the large Hadron collider (LHC), require the TDC to achieve a high time resolution in harsh environments with high tem perature and radiation, where the threshold voltage, transconductance, and delay of a transistor undergo dramatic changes. In these cases, the high accu racy and robustness of the TDC need to be inherent to the design rather than by employing a fast CMOS technology.