• DocumentCode
    2896585
  • Title

    An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling

  • Author

    Byun, Gyung-Su ; Kim, Yanghyo ; Kim, Jongsun ; Tam, Sai-Wang ; Hsieh, H.-H. ; Wu, P.-Y. ; Jou, C. ; Cong, Jason ; Reinman, Glenn ; Chang, Mau-Chung Frank

  • Author_Institution
    Univ. of California, Los Angeles, CA, USA
  • fYear
    2011
  • fDate
    20-24 Feb. 2011
  • Firstpage
    488
  • Lastpage
    490
  • Abstract
    In summary, we have designed and fabricated a DBI for mobile DRAM I/O interface in 65nm CMOS to obtain an aggregate data throughput of 8.4Gb/s and 10Gb/s on FR4 and Roger test boards, respectively, with power consumptions of 21 mW and 25mW. The BERs for both test boards are measured as <;1x10-15 by using 223-1 PRBS from the Agilent-70843C.
  • Keywords
    DRAM chips; high-speed integrated circuits; aggregate data throughput; mobile DRAM I/O interface; mobile memory I/O interface; simultaneous bidirectional dual band signaling; Aggregates; Bandwidth; Baseband; Mobile communication; Radio frequency; Random access memory; Transceivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-61284-303-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2011.5746409
  • Filename
    5746409
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2896585