Design and Implementation of a Low-power Baseband-system for RFID Tag

This article describes a low power design approach for a UHF passive RFID tag baseband system. It proposes a new RFID tag baseband architecture which is compatible with the EPC C1G2 UHF RFID protocol. Advanced low power design approaches are adopted, including separating driving clocks, applying an improved Tausworthe sequence generator, moving window PIE decoding algorithm, idle scheme and parallel operating scheme. The tag supports three commands, which are read, write and query. It consists of a 136 bits one-time programmable memory, rectifier, charge pump, clock divider, analog frontend and baseband system. SimuLink co-verification approach is applied for system functional test. The chip was designed and fabricated successfully by using 0.18 mum 6 layers CMOS technology