An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects

Current FPGA interconnect networks occupy the major area in FPGAs. The scalability problem has become a bottleneck towards the next-generation FPGA of even larger logic capacity. To relieve this problem, the idea of using FPGA interconnects in a time-multiplexed way has been previously proposed. However, the architecture and its design flow have not been studied before. In this paper, we describe a novel time-multiplexed FPGA interconnect architecture and the corresponding global routing algorithm, TMRouter. Based on PathFinder, TMRouter routes the circuit with time-sharing the wire segments. Experiments show that, for 16 large MCNC benchmark circuits, the minimum channel widths and critical path delays achieved by the TMRouter are 48.70% and 11.90% in average less than those of the VPR router, respectively.