Time-space energy consumption modeling of dynamic reconfigurable coarse-grain array processor datapath for wireless applications

The power consumption is a key aspect when designing a handheld device. Even when cycle accurate instruction set simulators for the ASIPs used in SDRs are existing to evaluate the performance of given mapping, the power consumption is evaluated only in the later phase during gate-level simulation. In this paper we propose an automatic way how to obtain dynamic energy consumption per opcode activation of an ASIP baseband-processor of our SDR platform. We use the results obtained for time-space energy consumption modeling of dynamic reconfigurable CGA processor datapath at the instruction set simulator level that we demonstrate on WLAN 2×2 40MHz application. The results allow us to propose important application and architectural changes for our ASIP.