DocumentCode
2896727
Title
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology
Author
Lee, Hyun-Woo ; Kim, Ki-Han ; Choi, Young-Kyoung ; Shon, Ju-Hwan ; Park, Nak-Kyu ; Kim, Kwan-Weon ; Kim, Chulwoo ; Choi, Young-Jung ; Chung, Byong-Tae
Author_Institution
Hynix Semicond., Icheon, South Korea
fYear
2011
fDate
20-24 Feb. 2011
Firstpage
502
Lastpage
504
Abstract
This paper introduces the first ever dynamic voltage scaling (DVS) technique for DRAM considering both the process skew and the operating frequency which is adopted for the consumer DDR2 SDRAM. The self-dynamic voltage scaling (SDVS) itself is a very powerful technique to stretch the battery life and increase the reliability of DRAM.
Keywords
CMOS memory circuits; DRAM chips; integrated circuit design; integrated circuit reliability; low-power electronics; CMOS technology; DDR2 SDRAM; DRAM reliability; battery life; bit rate 1.4 Gbit/s; consumer DRAM; operating frequency; process skew; self dynamic voltage scaling technique; size 44 nm; voltage 1.6 V; Bandwidth; CMOS technology; Clocks; Delay; Random access memory; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-61284-303-2
Type
conf
DOI
10.1109/ISSCC.2011.5746416
Filename
5746416
Link To Document