MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV

Author

Azevedo, Arnaldo ; Zatt, Bruno ; Agostini, Luciano ; Bampi, Sergio

Author_Institution

Microelectron. Group, UFRGS, Porto Alegre

fYear

2007

fDate

27-30 May 2007

Firstpage

1617

Lastpage

1620

Abstract

This paper presents the MoCHA (motion compensation hardware architecture) design. MoCHA is an architectural design for bi-predictive motion compensation of the H.264/AVC decoder. The designed architecture features a memory hierarchy to reduce the memory bandwidth and the number of memory access cycles. The architecture uses a single datapath to process bi-predictive reference areas and it processes luma and chroma samples in parallel. The design was mapped to a Xilinx Virtex II Pro FPGA and it is able to run at 100MHz. The throughput is enough to support more than 30 bi-predictive HDTV frames per second.

Keywords

field programmable gate arrays; high definition television; logic design; motion compensation; video codecs; video coding; 100 MHz; H.264/AVC decoder; HDTV; MoCHA; Xilinx Virtex II Pro FPGA; bi-predictive motion compensation hardware; bi-predictive reference areas; chroma samples; field programmable gate arrays; luma samples; memory access cycles; memory bandwidth; memory hierarchy; motion compensation hardware architecture design; Automatic voltage control; Decoding; HDTV; Hardware; IEC standards; ISO standards; Microelectronics; Motion compensation; Pipelines; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378828

Filename

4252964