Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS

This paper presents the complexity analysis of bit parallel multiplier in polynomial basis on FPGAs, both without and with carry logic. We directly present the Look-Up-Table (LUT) complexity and estimate the resource upper bound based on the existed gate-oriented architectures. Experimental results show that no FPGA synthesis tool reaches the estimated upper bound. Furthermore, the area optimization with fast carry logic can save additional 17% resources. The implementation results with manually mapped design on a Xilinx Virtex-4 device are reported.