Title :
A Design of DC Offset Canceller using Parallel Compensation
Author :
Oh, Seung-Min ; Park, Kyoung-Seok ; Yoo, Hyun-Hwan ; Na, Yoo-Sam ; Kim, Taek-Soo
Author_Institution :
IC Design Center, Samsung Electro-Mech. Co., Suwon
Abstract :
In this paper, a new DC offset canceller with parallel compensation is proposed based on the CMOS technology. Compared to the previously reported DC offset cancellers, the proposed topology can be implemented with the lower HPCF (high pass cutoff frequency) in the silicon substrate using same capacitance value. By utilizing the proposed DC offset canceller, an IF-VGA is designed for the direct conversion receiver and shows 1kHz of HPCF and 60dB of gain, while dissipating total current of 9mA from 1.8V supply with output buffer.
Keywords :
CMOS integrated circuits; intermediate-frequency amplifiers; radio receivers; 1 kHz; 1.8 V; 60 dB; 9 mA; CMOS technology; DC offset canceller; IF-VGA; direct conversion receiver; high pass cutoff frequency; parallel compensation; silicon substrate; variable gain amplifier; Bit error rate; CMOS technology; Capacitance; Circuits; Cutoff frequency; Digital video broadcasting; Energy consumption; Low pass filters; RF signals; Radio frequency;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.377917
