A Second Order ΔΣ Frequency Discriminator with Fractional-N Divider and Multi-Bit Quantizer

The analysis and design of a new ΔΣ frequency discriminator (FD) architecture is presented in this paper. This architecture has finer frequency resolution and lower noise compared to existing architectures. This superior performance is achieved by incorporating a fractional-N divider and a multi-bit quantizer. This new architecture is based on ΔΣ modulation techniques and converts instantaneous frequency directly to digital form. System level simulation models were developed in Matlab Simulink to explore the effects of various parameters on performance. The architecture was then partitioned into circuit blocks. Each of the circuit blocks was simulated at both the behavioural and the transistor level. This FD architecture is suitable for high resolution frequency synthesis.