Higher-level state machine based coverage analysis in RTL verification

Simulation is one of the most well-known methods for functional verification. The major problem of the simulation approach is to choose a good metric to deliver a high level of confidence in the hardware design. For example, sub-blocks of a wireless system, such as a channel decoder, consist of a data path and control unit. But most of these blocks can not be divided, exactly, into the data path part and the control part. Previous circuit-based metrics like FSM or data-path based metric are not efficient in these blocks. A higher level state machine model is proposed to replace the circuit-based coverage model in the coverage test. This higher-level state machine models one behavior or one operation as one state, so it is called a behavioral state machine (BSM). The state is identified by a condition statement such as if-then-else or case. This leads to the reduction of the number of state machines compared to previous FSM and consideration of data path coverage. Our examples show a performance comparison between our scheme and line code coverage.