DocumentCode
2897319
Title
Efficient parallelized particle filter design on CUDA
Author
Min-An Chao ; Chun-Yuan Chu ; Chih-Hao Chao ; An-Yeu Wu
Author_Institution
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2010
fDate
6-8 Oct. 2010
Firstpage
299
Lastpage
304
Abstract
Particle filtering is widely used in numerous nonlinear applications which require reconfigurability, fast prototyping, and online parallel signal processing. The emerging computing platform, CUDA, may be regarded as the most appealing platform for such implementation. However, there are not yet literatures exploring how to utilize CUDA for particle filters. This parer aims to provide two design techniques, A) finite-redraw importance-maximizing (FRIM) prior editing and B) localized resampling, for efficient implementation of particle filters on CUDA, which can be verified to reduce global operations and provide significant speedup. The modifications on algorithm and architectural mapping are evaluated with conceptual and quantitative analysis. From the classic bearings-only tracking experiments, the proposed design is 5.73 times faster than the direct implementation on GeForce 9400m.
Keywords
parallel processing; particle filtering (numerical methods); signal processing; CUDA; GeForce 9400m; finite redraw importance maximizing; online parallel signal processing; parallelized particle filter design; Accuracy; Atmospheric measurements; Computer architecture; Degradation; Graphics processing unit; Instruction sets; Particle measurements; CUDA; GPGPU; Particle filter;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems (SIPS), 2010 IEEE Workshop on
Conference_Location
San Francisco, CA
ISSN
1520-6130
Print_ISBN
978-1-4244-8932-9
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2010.5624805
Filename
5624805
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