• DocumentCode
    2897547
  • Title

    Architecture and finite precision optimization for layered LDPC decoders

  • Author

    Marchand, Cédric ; Conde-Canencia, Laura ; Boutillon, Emmanuel

  • Author_Institution
    NXP Semicond., Caen, France
  • fYear
    2010
  • fDate
    6-8 Oct. 2010
  • Firstpage
    350
  • Lastpage
    355
  • Abstract
    Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. In the practical hardware implementation of layered decoders, the performance is strongly affected by quantization. The finite precision model determines the area of the decoder, which is mainly composed of memory, especially for long frames. To be specific, in the DVB-S2,-T2 and -C2 standards, the memory can occupy up to 70% of the total area. In this paper, we focus our attention on the optimization of the number of quantization bits. Message saturation and memory size optimization are considered for the case of a DVB-S2 decoder. We show that the memory area can be reduced by 28% compared to the state-of-the-art, without performance loss.
  • Keywords
    decoding; digital video broadcasting; optimisation; parity check codes; DVB-S2 decoder; finite precision optimization; layered LDPC decoders; memory area; memory size optimization; message saturation; quantization bits; Decoding; Digital video broadcasting; Equations; Mathematical model; Parity check codes; Random access memory; Standards; DVB-S2; Low-density parity-check (LDPC) code; VLSI implementation; layered decoding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Systems (SIPS), 2010 IEEE Workshop on
  • Conference_Location
    San Francisco, CA
  • ISSN
    1520-6130
  • Print_ISBN
    978-1-4244-8932-9
  • Electronic_ISBN
    1520-6130
  • Type

    conf

  • DOI
    10.1109/SIPS.2010.5624816
  • Filename
    5624816