Title :
100GB/S two-iteration concatenated BCH decoder architecture for optical communications
Author :
Lee, Kihoon ; Kang, Han-Gil ; Park, Jeong-In ; Lee, Hanho
Author_Institution :
Sch. of Inf. & Commun. Eng., Inha Univ., Incheon, South Korea
Abstract :
This paper presents a two-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its high-speed low-complexity two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. A low-complexity syndrome computation architecture and a high-speed dual-processing pipelined simplified inversonless Berlekamp-Massey (Dual-pSiBM) key equation solver architecture were applied to the proposed concatenated BCH decoder with an aim of implementing a high-speed low-complexity decoder architecture. The proposed two-iteration concatenated BCH code structure with block interleaving methods allows the decoder to achieve 8.91dB of net coding gain performance at 10-15 decoder output bit error rate to compensate for serious transmission quality degradation. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s optical communications.
Keywords :
BCH codes; concatenated codes; error correction codes; error statistics; iterative decoding; optical communication; BCH codes; bit error rate; bit rate 100 Gbit/s; block interleaving methods; concatenated codes; error correction code; iteration decoding; optical communication; syndrome computation architecture; Bit error rate; Clocks; Complexity theory; Computer architecture; Decoding; Hardware; Polynomials; 100G; BCH; FEC; concatenated codes; decoder; low complexity; optical communications;
Conference_Titel :
Signal Processing Systems (SIPS), 2010 IEEE Workshop on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-8932-9
Electronic_ISBN :
1520-6130
DOI :
10.1109/SIPS.2010.5624879