Metal line and via electromigration improvement with wafer level tests

In semiconductor, the reliability of interconnects is assessed through electromigration (EM) on specially-designed metal line and via test structures. There are different types of test structures and methodologies for qualification and process monitoring purposes. Packaged level constant current EM (PLR EM) test is a widely accepted method for technology qualification. Wafer level accelerated tests such as Standard Wafer Electromigration Accelerated Test (SWEAT) and Isothermal method (ISOT) are also used to assess the metallization system. However, these methods are normally limited to monitoring and tool comparison when process is stable with enormous baseline data. This paper demonstrates the use of SWEAT and ISOT for process improvement. During technology developments, bimodal behavior of EM lifetime distribution was observed for via test structures. In order to optimize the time spent for testing and cost as well as to solve the PLR EM limited test capacity constraint, the SWEAT and ISOT tests were selected to identify the areas of improvement. These methods have successfully shortened the problem solving process and reduced the expensive long PLR EM test. The EM lifetime has been improved by changing the barrier metal and via glue processes.