DocumentCode
2898067
Title
A consideration on the Electrical Overstress(EOS) failure mechanism in the interconnection system of liquid crystal display(LCD) panel
Author
Kim, Jae-Hyung ; Kim, Dong-Nam ; Jang, Ho-Cheol ; Jo, Young-Chul ; Kim, Nam-Yong ; Kang, Seung-Geun ; Lee, Byung-Ju ; Kim, Dal-Soo
Author_Institution
TLi, Inc., Seongnam, South Korea
fYear
2010
fDate
Nov. 30 2010-Dec. 2 2010
Firstpage
1
Lastpage
4
Abstract
The IC industry has been paid a large amount of quality cost for Electrical Overstress(EOS) damages. This paper described the failure analysis procedure to find EOS source and the experimental methodology to verify the failure mechanism in the subsystems of the LCD panel interconnected with printed circuit boards.
Keywords
failure analysis; liquid crystal displays; printed circuits; EOS source; electrical overstress failure mechanism; failure analysis; interconnection system; liquid crystal display panel; printed circuit boards; Earth Observing System; Electrostatic discharge; Failure analysis; Integrated circuits; Pins; Surge protection; Surges;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Manufacturing Technology Symposium (IEMT), 2010 34th IEEE/CPMT International
Conference_Location
Melaka
ISSN
1089-8190
Print_ISBN
978-1-4244-8825-4
Type
conf
DOI
10.1109/IEMT.2010.5746676
Filename
5746676
Link To Document