A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter

A 10-b 30-MS/s low power CMOS pipelined analog-to-digital converter (ADC) is described. A low-voltage technique is proposed for pipelined analog-to-digital converter that avoids the use of on-chip clock voltage doubler, multithreshold voltage process, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough and enhance the dynamic performance of the pipelined ADC. The cross-coupled configuration of multiplying digital-to-analog converter (MDAC) also provides an effective common-mode feedback to overcome the problem of common-mode accumulation. This design achieves DNL and INL of 0.38LSB and 0.46LSB respectively, while SNDR is 58.5dB and SFDR is 66.1dB at an input frequency of 12MHz. Operating at 30MS/S sampling rate under a single 1.5V power supply, the power consumption is 36.8mW in a 0.35 mum CMOS process. Simulations have been performed to demonstrate the feasibility of this new technique.